TOP
R1
R2
C1
MCU-32
RAM
FPGA
ASIC
I/O CTRL
U1
U2
U3
U4
U5
ARCHITECTURE rtl OF alu IS
BEGIN
PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
acc <= (OTHERS => '0');
ELSIF rising_edge(clk) THEN
acc <= acc + operand;
END IF;
END PROCESS;
END rtl;
module alu #(parameter W=32)(
input logic clk, rst_n,
input logic [W-1:0] a, b,
output logic [W-1:0] y);
always_ff @(posedge clk)
if (!rst_n) y <= '0;
else y <= a + b;
endmodule
#!/bin/tcsh -f
setenv TOP alu
foreach f (*.sv)
vlog $f
set top alu
foreach f [glob *.v] {
vlog $f }
VHDL
SYSTEMVERILOG
TCSH
TCL
A B Cin
=1 &
=1 &
≥1
Sum Cout
1-BIT FULL ADDER
0040: 8B 44 24 04 89 04 24
0048: 03 44 24 08 C3 90 90
HEX
10 PRINT "HELLO"
20 GOTO 10
BASIC
MOV EAX, [ESP+4]
ADD EAX, [ESP+8]
RET
ASM
int add(int a, int b) {
return a + b;
}
C++
int add(int a, int b) {
return a + b;
}
JAVA
def add(a, b):
return a + b
PYTHON
const add = (a, b) => a + b;
JAVASCRIPT
FROM BASIC
One engineer's lifelong journey through countless languages —_
▼ scroll to boot ▼